The present invention relates to a high-voltage semiconductor device and a method of fabricating the same, and more particularly, to a high-voltage semiconductor device having a superjunction structure that is obtained by alternately forming impurity layers of different types of conductivity.
Conventionally, a high-voltage semiconductor device, such as a power metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), includes a source region and a drain region that are disposed on a top surface and a bottom surface, respectively, of a semiconductor body. Also, the high-voltage semiconductor device includes a gate insulating layer, which is disposed on the top surface of the semiconductor body adjacent to the source region, and a gate electrode, which is disposed on the gate insulating layer.
When the high-voltage semiconductor device is turned on, the semiconductor body provides a conductive path through which a drift current flows from the drain region to the source region. Also, when the high-voltage semiconductor device is turned off, the semiconductor body provides a depletion region that expands in a vertical direction due to an applied reverse bias voltage. The characteristics of the depletion region provided by the semiconductor body determine the breakdown voltage of the high-voltage semiconductor device.
In the above-described high-voltage semiconductor device, in order to minimize loss of conduction in a turn-on state and increase a switching rate, a vast amount of research has been conducted on reducing the turn-on resistance of the semiconductor body that provides the conductive path. Conventionally, one skilled in the art knows that the turn-on resistance of the semiconductor body may be reduced by increasing the concentration of impurities in the semiconductor body.
However, when the concentration of impurities in the semiconductor body is increased, space charges increase in the semiconductor body thus, lowering the breakdown voltage of the high-voltage semiconductor device. In order to overcome this drawback, various high-voltage semiconductor devices having a superjunction structure have been proposed. One known high-voltage semiconductor device with a superjunction structure is shown in FIG. 1.
Referring to FIG. 1, high-voltage semiconductor device 100 includes a superjunction that is obtained by alternately forming an N-type impurity region (referred to as an N-type pillar 21) and a P-type impurity region (referred to as a P-type pillar 22) in a horizontal direction. Each of the N-type pillars 21 and the P-type pillars 22 extend in a vertical direction in a semiconductor layer 60 disposed on a semiconductor substrate 10. A lightly doped P-type well region 30 is disposed in semiconductor layer 60, and a heavily doped N-type source region 40 is disposed in the lightly doped P-type well region 30 over the semiconductor layer 60. A source electrode S is electrically connected to the heavily doped N-type source region 40. Also, the high-voltage semiconductor device 100 includes a gate stack 50, which is disposed on the semiconductor layer 60 adjacent to the heavily doped N-type source region 40. The gate stack 50 includes a gate insulating layer 51 and a gate electrode 52. Also, the semiconductor substrate 10 that is connected to a bottom surface of the semiconductor layer 60 functions as a drain electrode D.
When the high-voltage semiconductor device 100 is turned on, the N-type pillars 21 provide a conductive path through which charges flow from the source electrode S through a channel disposed under the gate stack 50 to the drain electrode D. When the high-voltage semiconductor device 100 is turned off, the N-type pillar 21 and the P-type pillar 22 are depleted due to a reverse bias voltage, so that the high-voltage semiconductor device can have a sufficiently high breakdown voltage.
Particularly, when the amount of charge of the N-type pillar 21 is balanced with the amount of charge of the P-type pillar 22, the N- and P-type pillars 21 and 22 are completely depleted in a turn-off state of the high-voltage semiconductor device 100 so that the N- and P-type pillars 21 and 22 may function as an ideal insulator. By considering a unit superjunction U (designated by a dotted quadrangle) comprised of half of the N-type pillar 21 and half of the P-type pillar 22 that are disposed adjacent to each other, Equation 1 below should be satisfied in order to balance the amount of charge of the N-type pillar 21 with the amount of charge of the P-type pillar 22.Nn×½Wn=Np×½Wp  (1)
wherein Nn denotes the dopant concentration of the N-type pillar 21, Np denotes the dopant concentration of the P-type pillar 22, Wn denotes the width of the N-type pillar 21, and Wp denotes the width of the P-type pillar 22.
As described above, when the amount of charge of the N-type pillar 21 is balanced with the amount of charge of the P-type pillar 22, a breakdown voltage may be determined by a product of the height H of the unit superjunction U and an electric field generated between the unit superjunctions U. As a result, even if the resistance of the high-voltage semiconductor device 100 is reduced by increasing the dopant concentration of the N-type pillar 21, since the resistivity of the N-type pillar 21 does not affect the breakdown voltage, a high breakdown voltage can be obtained.
In order to fabricate the high-voltage semiconductor device 100 having the conventional superjunction structure, for example, an N-type semiconductor layer 60 is formed using an epitaxial growth process on the semiconductor substrate 10, and the N-type semiconductor layer 60 is etched to form a trench in a region where the P-type pillar 22 will be formed. Thereafter, a P-type epitaxial layer is formed using, for example, a chemical vapor deposition (CVD) process, to fill the trench. In this process, a superjunction structure in which the N-type pillar 21 and the P-type pillar 22 are alternately formed may be fabricated.
However, because the superjunction structure has a height of several tens of μm to hundreds of μm and a width of several μm, it is difficult to form the trench having a precisely vertical sidewall in the semiconductor layer 60 using an etching process. Even if the trench having the vertical sidewall in the semiconductor layer 60 is formed, it is difficult to fill the trench with an epitaxial layer given the high aspect ratio of the trench.
When the sidewall of the trench formed using an anisotropic etching process forms an angle δ less than 90°, the P-type pillar 22 tapers in a depthwise direction of the semiconductor layer 60. As a result, the amount of charge of the P-type pillar 22 gradually decreases in the depthwise direction thereof, and the amount of charge of the N-type pillar 21 relatively increases in the depthwise direction thereof and thus, the charge balance cannot be maintained in the unit superjunction U. The charge imbalance in the unit superjunction U worsens as the angle δ formed by the sidewall of the trench decreases and thus, a breakdown voltage decreases.